Local and global planarization of semiconductor wafers becomes increasingly important as more metal layers and interlayer dielectric layers are stacked on the wafers. A preferred method to planarize semiconductor wafers is the chemical mechanical polishing (CMP) method, where a surface of a semiconductor wafer is polished using a slurry solution supplied between the wafer and a polishing pad. The CMP method is also widely used for damascene process to form copper (Cu) interconnect structures on the semiconductor wafers.
As illustrated in FIG. 1A, in order to form a Cu damascene structure using a conventional CMP method, a semiconductor wafer 10 having a dielectric layer 12 with trenches, a barrier metal layer 14 and a Cu layer 16 is fabricated. The Cu layer 16 is then polished using a first continuous CMP process at a first polishing unit of a polishing apparatus until the barrier layer 14 on the upper surface of the dielectric layer 12 is exposed to remove the Cu layer above the barrier layer. Next, the barrier layer 14 on the upper surface of the dielectric layer 12 is polished at a second polishing unit of the polishing apparatus using a second CMP process to remove the barrier layer on the upper surface of the dielectric layer, which results in the semiconductor wafer 20 with the Cu damascene structure, as illustrated in FIG. 1B.
In an another conventional CMP method, the Cu layer 16 is polished using first and second serial CMP processes at first and second polishing units of a polishing apparatus, respectively, to remove the Cu layer above the barrier layer 14 until the barrier layer on the upper surface of the dielectric layer 12 is exposed. Next, the barrier layer 14 on the upper surface of the dielectric layer 12 is polished at a third polishing unit of the polishing apparatus using a third CMP process to remove the barrier layer on the upper surface of the dielectric layer, which results in the semiconductor wafer 20 with the Cu damascene structure, as illustrated in FIG. 1B.
A concern with the conventional CMP methods for forming a Cu damascene structure is that the resulting Cu damascene structure will typically have a non-planar erosion topography 22, as illustrated in FIG. 1B, which can significantly degrade the final semiconductor device. This erosion topography 22 is formed during the process of removing the Cu layer 16, the barrier metal layer 14 or both of the layers.
Another concern with the conventional CMP methods is that the throughput of the polishing apparatus with two or three polishing units drops drastically for Cu damascene structures that require removing a thicker portion of the Cu layer over the barrier metal layer. It is noted that the thicker the Cu layer to be removed is, the polishing times of the respective polishing units become more unbalanced, and therefore, the last polishing unit of the polishing apparatus to remove the barrier metal layer idles while the other polishing units polish the Cu layers.
In view of these concerns, there is a need for methods for fabricating one or more Cu damascene structures in a semiconductor wafer that reduce erosion topography of the Cu damascene structures and/or increase throughput.